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SP9316
Corporation
SIGNAL PROCESSING EXCELLENCE
16-Bit CMOS Multiplying DAC
s s s s s s High Stability with No Laser-Trimming 15-Bit Monotonicity over Temperature Single Power Supply Operation Upper/Lower Byte Input Registers 2- and 4-Quadrant Multiplication 60mW Power Dissipation
DESCRIPTION... The SP9316 is a 16-bit, monolithic CMOS, multiplying digital-to-analog converter with two 8-bit input registers for direct microprocessor interface. It offers two- and four-quadrant multiplying capability with TTL/DTL and CMOS logic compatibility. Operating from a single +15V supply, power dissipation is less than 60mW. The SP9316 is packaged in 24-pin ceramic or molded plastic. Models are available for operation over the commercial (0C to 70C) and military (-55C to +125C) temperature ranges. For product screened to MIL-STD-883, please consult the factory.
BIT: 9 10 11 12 13 14 15 16 4 LSB LATCH CONTROL REFERENCE INPUT MSB LATCH CONTROL 19 13 20 5 BIT: 8 3 2 1 24 23 22 21
ANA GND 18
+15V 17 SP9316 15 16 14 5K IOUT2 IOUT1 FEEDBACK
INPUT REGISTER PRECISION 16-BIT RESISTOR NETWORK & SWICHES INPUT REGISTER 6 7 7 6 8 5 9 4 10 11 12 3 2 1(MSB)
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ABSOLUTE MAXIMUM RATINGS
(TA=25C unless otherwise noted) These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD to GND ................................................................. --0.3V, +17V Digital Input Voltage to GND ............................... --0.3V ,VDD +0.3V
VREF or VRFB to GND ................................................................ 25V Output Voltage (Pin 15, Pin 16) ........................... -0.3V, VDD +0.3V Power Dissipation (Any Package) to +75C ........................ 450mW Derates above 75C by ...................................................... 6mW/C Dice Junction Temperature ................................................. +150C Storage Temperature .......................................... --65C to +150C
SPECIFICATIONS
(TA=25C; VDD =+15V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER MIN. TYP. STATIC PERFORMANCE Resolution 16 Integral Non-Linearity C-4 B-4 Differential Non-Linearity C-4 B-4 Offset Error Gain Error 0.1 AC PERFORMANCE CHARACTERISTICS Propagation Delay 300 Current Settling Time To 0.01% FSR (strobed) 2.0 To 0.00076% FSR (strobed) 3.0 Output Capacitance CO1 170 CO2 30 CO3 80 CO4 100 Glitch Energy 250 Multiplying Feedthrough Error 3.0 0.3 STABILITY All Grades: Gain Error TC 1.0 Offset Integral Non-Linearity TC 0.1 Monotonicity Guaranteed C-4 14 B-4 14 Power Supply Rejection LONG-TERM STABILITY Differential Non-linearity Offset Gain REFERENCE INPUT Input Impedance 2.5 Voltage Range -10 SWITCHING CHARACTERISTICS Strobe Width 80 Data Setup Time 80 Data Hold Time 40
MAX.
UNIT Bits
CONDITIONS
0.006 0.006 0.006 0.006 60 0.2
Note 5 %FSR %FSR Note 7 %FSR %FSR V %FSR ns s s pF pF pF pF nV-s mVP-P mVP-P Note 3 Note 4 Note 9 Major code settling times
Digital input VIH Digital input VIH Digital input VIL Digital input VIL Note 10 Note 11 Note 12 Note 4 Note 6 Note 5
4.0 1.0 1.0 1.0
ppm/C ppm/C ppm/C ppm/C Bits Bits %/% ppm/C ppm/C ppm/C
0.0001 1 0.5 1 5.0
0.002
VDD = 14.0V to 16.0V
7.5 +10
K Volts ns ns ns
60 70 20
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SPECIFICATIONS (continued)
(TA=25C; VDD =+15V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER MIN. TYP. MAX. DIGITAL INPUTS Logic Levels VIH 2.4 VDD VIL -0.3 0.8 Input Current 1.0 10.0 Input Capacitance 8 Coding 2-Quadrant Unipolar Binary 4-Quadrant Bipolar Offset Binary ANALOG OUTPUT Small Signal -3dB Bandwidth 1 Output Capacitance COUT1 90 COUT2 70 POWER REQUIREMENTS Supply Current 2.0 4.0 Voltage Range VDD +5 +15 +16 Power Dissipation 60 ENVIRONMENTAL AND MECHANICAL Operating Temperature Commercial 0 +70 Military -55 +125 Storage Temperature -65 +150 Package Commercial 24-pin Plastic DIP Military 24-pin CerDIP
UNIT
CONDITIONS
Volts Volts A pF
Note 1 Note 2
MHz pF pF mA Volts mW DIG IN = VIL or VIH DIG IN = VIL or VIH
C C C
Notes and Cautions: 1. Logic inputs are MOS gates. IIN typically is less than 1nA @ 25C. 2. Guaranteed by design, but not production tested. 3. Unipolar: Using the internal RFEEDBACK with nulled external amplifier in a constant 25C ambient (offset doubles every 10C). 4. Using internal feedback resistor. 5. Integral Linearity, for this product, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input combination. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 6. The SP9316 series is designed to be used only in those applications where the current output is virtual ground; i.e. the summing junction of an op amp in the inverting mode. The internal feedback resistor must be used to achieve temperature tracking. See applications information for recommended circuit configurations. 7. For military temperature range product, screened to MIL-STD-883C, please consult the factory. 8. Sample tested only to ensure compliance. 9. IO1 load RL = 100, CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of final analog output. 10. VREF = 0V, DAC register alternatively loaded with all 0's and all 1's. 11. Measured at output IO1; VREF = 20VP-P; F = 10kHz sinewave. 12. Measured at output IO1; VREF = 20VP-P; F = 1kHz sinewave.
0.000
Parameter Change (% FSR)
0.002 0.004 0.006 0.008 0.010 0 1 2 3 4 5 Warm-Up Time(Minutes)
Error in LSB's
1.0 0.5 Typical @ 25C and +15V nominal
-10
-5
0 VREF (Volts)
+5
+ 10
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PIN ASSIGNMENTS Pin 1 -- DB12 -- Data Bit 12. Pin 2 -- DB11 -- Data Bit 11. Pin 3 -- DB10 -- Data Bit 10. Pin 4 -- DB9 -- Data Bit 9. Pin 5 -- DB8 -- Data Bit 8. Pin 6 -- DB7 -- Data Bit 7. Pin 7 -- DB6 -- Data Bit 6. Pin 8 -- DB5 -- Data Bit 5. Pin 9 -- DB4 -- Data Bit 4. Pin 10 -- DB3 -- Data Bit 3. Pin 11 -- DB2 -- Data Bit 2. Pin 12 -- DB1 -- Data Bit 1 (MSB). Pin 13 -- VREF In -- Voltage Reference Input. Pin 14 -- RFB -- Feedback Resistor. Pin 15 -- IOUT2 -- Current Output. Pin 16 -- IOUT1 -- Inverted Current Output. Pin 17 -- VDD -- +15V Power Supply. Pin 18 -- GND -- Analog GND. Pin 19 -- LSB LATCH -- LSB Latch control. Level-triggered. Data is latched with strobe at logic 0; logic 1 allows data to update DAC directly.
Pin 20 -- MSB LATCH -- MSB Latch control. Level-triggered. Logic 0 strobes data into latch; logic 1 allows data to update DAC directly. Pin 21 -- DB16 -- Data Bit 16 (LSB) . Pin 22 -- DB15 -- Data Bit 15. Pin 23 -- DB14 -- Data Bit 14. Pin 24 -- DB13 -- Data Bit 13.
FEATURES... The SP9316 is a 16-bit, monolithic CMOS, multiplying digital-to-analog converter with two 8-bit input registers for direct microprocessor interface. It offers two- and four-quadrant multiplying capability with TTL/DTL and CMOS logic compatibility. It is ideally suited for Automated Test Equipment, medical instrumentation and high-energy physics applications. Operating from a single +15V supply, power dissipation is less than 60mW. High accuracy and monotonicity are achieved without laser-trimming through the use of a highly accurate, low- TCR thin-film resistor process. A unique digital decoding technique of the 4 MSB's results in excellent linearity and stability over both time and temperature. The SP9316 is packaged in hermetic 24-pin ceramic or molded plastic. Models are available for operation over the commercial (0C to 70C) and military (-55C to +125C) temperature ranges. For product screened to MIL-STD-883, please consult the factory.
400 VREF 13 17 GND 18 BIT 1 (MSB) RFB DIGITAL INPUT SP9316 IOUT1 16 _ A IOUT2 15 + All "ones": VOUT = -VREF + 1LSB VOUT 14 ROS +15V 0.01F + 1F
BIT 16 (LSB) MSB LATCH LSB LATCH
NOTE: To maintain specified linearity, the external amplifier (A) must be nulled. Apply an "all zeroes" digital input and adjust ROS for VOUT = 01mV.
Figure 1. Unipolar Operation
USING THE SP9316 General Configuration The SP9316 can be configured for unipolar voltage operation (2-quadrant multiplication) or bipolar voltage operation (4-quadrant multiplication.) Coding is binary and offset binary respectively. In bipolar operation both the reference signal and the number represented by the digital input applied to the SP9316 may be of either positive or negative polarity.
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Individual latch controls are provided for the high and low bytes which may be tied together for a single 16-bit word update. The data is latched with the strobe at logic 0. The latches are level-triggered and can be made transparent by tying them to logic 1. However, use of the latches is recommended in most applications as they significantly reduce data bit skew, which affects the glitch performance. Layout, Grounding and Guarding 16-bit system performance can be maintained with suitable attention paid to the layout, grounding and guarding techniques employed. All grounds should be of as low resistance as possible. Analog and digital grounds should be individually star-pointed and tied together as close as possible to the SP9316. Good layout techniques dictate that the high-speed digital inputs should be kept separate from low-level analog outputs. The DAC output and op amp input are high impedance and so are sensitive to interference from the digital input lines. Careful pinout design of the SP9316 has reduced this problem to a minimum, but guarding of these points should be considered. Figures 3 and 4 detail the low impedance guard track layout. Amplifier Selection The SP9316 allows the designer to obtain the optimum performance for each application. Selection of the correct operational amplifier, and the layout of the associated components are critical to the success of the design. To obtain the optimum linearity performance, the amplifiers must have an open loop gain in excess of 100,000 or 100dB. Care should be taken to
400 VREF 13 17 GND 18 BIT 1 (MSB) RFB DIGITAL INPUT SP9316 IOUT1 16 _ R BIT 16 (LSB) MSB LATCH LSB LATCH A1 IOUT2 15 + VO1 + All "ones": VOUT = -VREF + 1LSB _ A2 VOUT 14 ROS1 R for 5V FS output 2R for 10V FS output ROS2 +15V 0.01F + 1F 2R
Binary Input 111...111 100...001 100...000 011...111 000...001 000...000
Analog Output -V (1-2 ) -V ( +2 ) -V ( ) -V ( -2 ) -V (2 ) 0
N REF -N REF REF -N REF -N REF
Table 1. Unipolar Transfer Function
ensure that the summing junction is as close to analog ground as possible. Most applications demand that the input offset be kept below 100V. To maintain accuracy over temperature, the amplifiers should have low bias currents and offset voltage temperature coefficients. In bipolar applications, attention must be paid to the choice of resistors R and 2R (see figure 2). As the analog voltage output increases from zero to full-scale, the power dissipated by the feedback resistor increases and the resistor heats up. This causes a small change in the resistance value which could lead to an alteration to the transfer function, which may be seen as integral linearity errors. The internal resistor network has been designed using ultra-stable thin-film nichrome. It is important that the temperature coefficient of the external resistors match those in the DAC as closely as possible. Resistors with a temperature coefficient of 10ppm/C or better should be used. LONG TERM DRIFT When measuring the stability of the SP9316, great care should be taken to ensure that the drift of the measurement instruments can be sepaOffset Binary Input 111...111 100...001 100...000 011...111 000...001 000...000 Analog Output -V (1-2 ) -V (2 ) 0 V (2 ) V (1-2 ) V
-(N-1) REF -(N-1) REF -(N-1) REF -(N-1) REF REF
NOTE: To maintain specified linearity, the external amplifiers (A1 and A2) must be nulled. With a digital input of 10...0 and VREF set to zero -- 1) set ROS1 for VO1 = 0V; 2) set ROS2 for VOUT = 0V; 3) set VREF to +10V and adjust RB for VOUT = 0V
Figure 2. Bipolar Operation
Table 2. Bipolar Transfer Function
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SP9316 14 RFB IOUT1 IOUT2 16 15
+
VREF SP9316 RFB 14
VOUT Guard
IOUT1 16 IOUT2 15
+ +
VOUT
Guard
Figure 3. Unipolar Guarding
Figure 4. Bipolar Guarding
rated from the device drift, and that all measurements are taken at identical temperatures. The long-term drift of the SP9316 voltage output system transfer function, after initial op amp trim, will largely be determined by the choice of the external components. For minimum offset error the op amps should be trimmed after one hour of continuous operation. The SP9316 contribution to the offset drift after that time will be 0.1ppm/C per 1000 hours. The long-term gain drift error contribution of the SP9316 is 1 ppm/C per 1000 hours. Also to be considered are the temperature coefficients of the external resistors, the op amp drift specifications and the stability of the reference. The SIPEX HS2700LD, with a stability drift of 3ppm/C, is recommended as a suitable voltage reference. The unique segmented architecture of the SP9316 resistor network, plus the low-TCR nichrome materials and processes used in its manufacture, results in an exceptionally low linearity drift with time. Typical differential linearity drift with temperature is 0.1ppm/C.
APPLICATION Digitally-Controlled Low Pass Filter The SP9316 can be used to construct active filters which display very low noise and distortion characteristics. Low pass filters can be designed to provide digital control over center frequency, gain and Q-factor. The SP9316 is an ideal high resolution element for this application. Figure 5 shows a low-pass filter designed to be independent of the resistance of the SP9316 network by using it as a programmable gain element. The filter characteristic is given by:
VOUT = -R3 VIN R1
(
1 R3R4C 1+ j R2D
(
)
)
where D is the binary code applied to the DAC and C is the value of the capacitor.
R3 +5V 4 BIT: 9 R1 VIN - A1 + R2 19 LSB LATCH CONTROL 13 REFERENCE INPUT 20 MSB LATCH CONTROL BIT: 8 5 3 2 1 24 23 22 21 18 10 11 12 13 14 15 16 ANA GND INPUT REGISTER PRECISION 16-BIT RESISTOR NETWORK & SWICHES INPUT REGISTER 7 6 6 7 5 8 4 9 3 2 1(MSB) 5K 10 11 12 17 +15V VOUT = -R3 VIN R1 15 16 14 - A2 + + R4 - A3 VOUT
SP9316 IOUT2 IOUT1 FEEDBACK
(
1 RC 1+ j R3 4 R2D
(
)
)
C
Figure 5. Digitally-Controlled Low-Pass Filter
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DATA t1 LATCH t2 OUTPUT
VALID DATA t1
VALID DATA
t2
t1 = Data Setup Time (80ns) t2 = Strobe Width (80ns) t3 = Settling Time (2s typical)
t3
Figure 6. Timing
Ordering Information
Model ............................................................................. Linearity .............................................................................................................. Package 0C to +70C: SP9316C-4 .................................................................. 14-Bit Linearity .............................................................................. 24-pin, 0.6" Plastic DIP -55C to +125C, MIL-STD-883C Screened: SP9316B-4 .................................................................. 14-Bit Linearity .................................................................................... 24-pin, 0.6" CerDIP
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